资源列表
fifo_ctrl
- fifoctr 寄存器控制 verilog代码-FIFO ctr
spi_master
- SPI master code: generates CS and tx/rx data
bpsk1
- 上传的包括BPSK,AGC,LCD1602和12846的显示代码和一个自己写的1602内核，代码全部得到验证，都可以使用！-Uploaded including BPSK, AGC, the LCD1602 and 12846 display code and a 1602 write kernel code all been verified, you can use!
Digital-Clock
- FPGA数字跑表代码 Digital Clock-Digital Clock
FIFO
- 异步FIFO设计 FPGA代码 Asynchronous fifo-Asynchronous fifo
11_lcd1602
- 这是一个fpga的lcd1602显示的代码，代码是用verilog语言写的，经过编译后成功了，-This is the fpga' s lcd1602 displayed code, code verilog language written successfully compiled,
Pseudo-random
- 伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
12_lcd12864
- 和上面上传的资料一样，这次上传的是12864的显示代码，也是用fpga实现的，当然也是绝对正确的代码-And upload the above information, this time to upload the display code is 12864, is also using fpga, of course, absolutely right code
Multiplier
- 一个乘法器的FPGA设计代码 Multiplier-fpga Multiplier
Divider
- 一个除法器的FPGA代码设计 Divider-fpga Divider
Adder
- 一个加法器的FpGA设计代码 fpga adder-fpga adder
15_tlc5620dac
- 这是芯片tlc5420数字模拟信号传换实验，实验是用verilog语言写的，希望对大家有用-This is the pass the chip tlc5420 digital-to-analog signal change experiment, experiment verilog language written in the hope that useful. . .