资源列表
13_vga256
- 这是fpga vga显示实验，实验是用verilog语言写的，经过，能够显示，希望对大家有用-Fpga vga experiments is written with verilog language is proven to be able to display the hope that useful. . .
sram_test
- SRAM read/write example
main_i2c
- the complete i2c core written in vhdl and tested on sparten 6 fpga
Digital-clock-design
- 用VHDL语言设计数字钟.实现以下功能：正常走表，时间设置，闹钟设置，整点报时，闹钟提醒。-Digital clock using VHDL language . Achieve the following functions: normal walking table, time settings, alarm settings, the whole point timekeeping, alarm.
parity_chk_32
- 这是一个32位的奇偶校验程序,VHDL代码,可用于FPGA.-32 bit parity check
parity_chk_32-
- 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
LCD_control
- VERILOG语言编写的LCD1602点阵屏的LCD控制器，用此模块可把MCU省掉，驱动屏幕变简单了-Dot matrix screen LCD controller VERILOG language LCD1602, this module MCU dispense driven screen easier
test
- ISE工程 包含各种基本部件 全加器 寄存器 解码器-The ISE project includes various basic components of the full adder register decoder
5fenpinqi
- 实现5分频的分频器程序，并且使用仿真文件进行测试通过。-5 frequency divider program, and tested through simulation file.
text6_1602
- 1602的VERILOG驱动，希望对你有用！-verilog HDL .v file for LCD1602 display
ss
- 智能车寻迹（PWM调速）和行驶时间显示，VHDL语言编写-Smart car tracing (PWM speed) and travel time
ceshiled
- de2-70上实现led灯流水线闪亮非常好的学习资料-achieve a led lamp pipeline shiny de2-70