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  1. cf_fft_latest.tar

    0下载:
  2. The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers. This FFT can perform calculations on continuous streaming data (one data set right after anot
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:2.98mb
    • 提供者:amin
  1. system05_latest.tar

    0下载:
  2. 6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:28.69kb
    • 提供者:amin
  1. fpu100_latest.tar

    0下载:
  2. This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard-This is a 32-bit floating
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.88mb
    • 提供者:amin
  1. zorro_to_wishbone_bridge_latest.tar

    0下载:
  2. This project intends to create a bridge between Wishbone and the Amiga Zorro II and Zorro III busses. As in the Amiga 3000/4000 computer families, it is intended to support both the Zorro II and Zorro III protocols at the same time on the same bus.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:9.82kb
    • 提供者:amin
  1. i2cslave

    0下载:
  2. 此代码是I2C Slave的Verilog源代码,已经经过上板调试,没问题。-This code is the I2C Slave of Verilog source code, has been on the board debugging, no problem.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:1.2mb
    • 提供者:Evan Xie
  1. YCbCr2RGB_O

    0下载:
  2. 此代码是把YUV转成RGB的Verilog程序,多谢下载-This code is to convert RGB to YUV Verilog program, thank you download
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:1.37kb
    • 提供者:Evan Xie
  1. sdram

    0下载:
  2. 文件中包含Sdram的Verilog程序以及很全的Sdram的资料-Sdram the Verilog file contains procedures and information are all of Sdram
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-24
    • 文件大小:3.55mb
    • 提供者:Evan Xie
  1. AlteraFPGACPLDcoder

    0下载:
  2. Altera FPGA/CPLD设计(基础篇)随书代码-Altera FPGA/CPLD design (fundamental) with the code book
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-26
    • 文件大小:8.38mb
    • 提供者:李磊
  1. AlteraFPGACPLDcoder2

    0下载:
  2. Altera FPGA/CPLD设计(高级篇)随书代码-Altera FPGA/CPLD Design (Senior Posts) With the written code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.19mb
    • 提供者:boto
  1. 100vhdlexamples

    0下载:
  2. 100个VHDL例子 比较全面 非常好的学习资料-100 VHDL very good example of a more comprehensive study materials
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:228.06kb
    • 提供者:boto
  1. vhdlbasicexamples

    0下载:
  2. VHDL 基础实例 范围广泛 非常值得学习-VHDL is based on a wide range of examples worth learning
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:49.8kb
    • 提供者:boto
  1. quartusIIexperimentguide

    0下载:
  2. QuartusII实验指导书FPGA设计初级班培训实验指导手册_V1..0pdf.pdfFPGA设计提高班培训实验指导手册_V1.0.pdf-QuartusII experimental instructions FPGA design training beginners guide _V1 .. 0pdf.pdfFPGA experimental design experiments to improve the training courses guide _V1.0.pdf
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:2.2mb
    • 提供者:李磊
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