资源列表
vhdlcodes2
- VHDL coding for a 4 bit comparator in structural and behavioural modelling.
vhdlcodes3
- VHDL coding for 2 to 4 decoder in dataflow modelling and for 4 bit parity checker in behavioural and for 3 bit parity generator in behavioural.
vhdlcodes4
- VHDL coding for 4X1 mux in behavioural modelling and for 16X1 mux in structural modelling.
SDRAM
- 对SDRAM的介绍非常详细，里面有很多对SDRAM的程序控制模块的设计。-Very detailed presentation on the SDRAM, which has many of the SDRAM of the process control module.
ControllingElevatorbyFPGACode.txt
- This code is talk about how to programming FPGA to control Elevator.
lab1code
- 时钟，可正计数，反记数，每分钟提示一次.时钟通过计数器实现，优化实现进位-a clock which can count on and count off. remain very minute
chap2_encode
- FPGA学习例程-VHDL语言实现的编码器-FPGA Encoder learning routines-vHDL
chap3_adder
- FPGA学习资料-VHDL语言实现的加法器-FPGA implementation of learning materials-VHDL Adder
chap5_voter5
- FPGA学习资料-VHDL语言实现的表决器-FPGA-VHDL language learning materials in the voting machine
chap8_CntStep
- FPGA学习资料-VHDL语言实现的计数器-FPGA-VHDL language learning materials counter
decode4_7
- 二进制译码器的一般结构图如图2.4所示，它具有n个输入端，2n个输出端和1个使能输入端。在使能输入端为有效电平时，对应每一组输入代码，只有其中一个输出端为有效电平，其余输出端则为相反电平。输出信号可以是高电平有效，也可以是低电平有效。-encode
voter7
- 二进制译码器的一般结构图如图2.4所示，它具有n个输入端，2n个输出端和1个使能输入端。在使能输入端为有效电平时，对应每一组输入代码，只有其中一个输出端为有效电平，其余输出端则为相反电平。输出信号可以是高电平有效，也可以是低电平有效。-encode