资源列表
FPGA_Architecture
- FPGA Architecture Power point presentation
xilinx_flow
- Xilinx Flow Power point Presentation
4x4_bits_Booth_Algorithm
- Verilog写的booth算法，是微机原理的基本算法，对Verilog的入门有帮助，包含代码和报告-Booth algorithm written in Verilog is the basic principle of computer algorithms, Verilog entry helpful, the report contains the code and
10bit_Booth_algorithm
- 10位加法器，booth算法对学习computer architecture有帮助-10-bit adder, booth algorithm is useful for learning computer architecture
booth4
- 4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写-4-bit adder booth algorithm, the learning of computer organization help, verilog language
LCD_SCREEN
- 利用了状态机的53种状态太分别描述LCD显示频的初始化、显示字符串“OK!”的时序图中的详细过程-Use of 53 states of state machine LCD display is too describe the frequency initialized, the string " OK!" The timing diagram of the detailed process
74hc4017
- 实现的是扭环形十进制计数器，用verilog HDL 语言，在Actel公司提供的LiberoFPGA开发环境下实现，代码经过验证，可在ModelSim中仿真 -Ring is twisted to achieve a decimal counter, using verilog HDL language, Actel offers the LiberoFPGA development environment, the code is validated, the simulation in t
ROM
- 本代码实现的是生成随机数的verilog 代码。可在ModelSim中仿真-The code is the verilog code to generate random numbers. In the simulation in the ModelSim
34342342432
- 基于FPGA的PCIE1接口设计与实现.pdf-the design and implmentation of PCI and E1 interface based on FPGA.
music
- 蜂鸣器实现播放音乐，两个按键可选择播放，共三首音乐可选。Xilinx ISE 9.1环境下工程。-Buzzer for playing music, playing the two keys to select a total of three songs optional. Xilinx ISE 9.1 environment projects.
ADC0809
- 基于VHDL语言，实现对ADC0809简单控制。ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟-Based on VHDL language, to achieve simple control of ADC0809. ADC0809 no internal clock, an external 10KHz ~ 1290Hz clock signal, where
Array_implementation_in_VHDL
- This code to make Array implementation in VHDL.-This is code to make Array implementation in VHDL.