资源列表
freqconv
- In digital signal processing, a digital down-converter (DDC) converts a digitized real signal centered at an intermediate frequency (IF) to a basebanded complex signal centered at zero frequency. In addition to downconversion, DDC’s typically decimat
debounce_logic
- This HDL Module take input from any mechanical switch and give the stable output without glitches.
SPCfilte
- 程控滤波器的设计文档，滤波芯片为ltc1068,程控放大器为ad603，采用FPGA产生DDS.-SPC filter design documents, ltc1068 chips for filtering, program-controlled amplifier for ad603, based on FPGA produce spurious.
Pipelined_CPU
- 此程序是关于MIPS的RSIC架构的带有流水线功能的源码，对于RSIC_CPU的初学者在理解RSIC系统上有很大的帮助。-This program is about the RSIC architecture MIPS pipelined function with source code, for novices to understand the RSIC RSIC_CPU system is very helpful.
h264_baseline_dec_ip_core
- 这是一个有关h264解码器的IP核源代码，内有对其内部各功能的整体说明。-This is a relevant h264 decoder IP core source code for its internal function within the overall descr iption.
i2c
- 这是一个关于I2C总线的源代码，内部含有VHDL和Verilog两种格式的代码。-This is a source code on the I2C bus, the internal VHDL and Verilog formats containing the code.
RedHurricane2Schematic
- altera红色飓风2电路的原理图，供各位参考-Red Hurricane 2 Schematic
trafic_light_controller
- verilog code for traffic light controller on altera kit epc16q240c8.
tutorial_switched_power
- Tutorial for switched power supply
PMACbeginerChinese
- PMAC的用法，在visual c++的环境下进行开发的使用说明。-PMAC usage, in the visual c++ development environment for instructions.
ASIC.and.FPGA.Verification.A.Guide.to.Component.Mo
- ASIC的FPGA模型设计，VHDL版 英文原版书籍-ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling.Morgan.Kaufmann
core
- VHDL编写的51单片机软核，支持在Modelsim下仿真，仿真可直接运行HEX文件，v0.1，后续版本还在开发中。 Craftor原创，仅供学习和交流使用。-51-compatible soft-core, written in VHDL, can be simulated in ModelSim and execute HEX file。 By Craftor