资源列表
shiyan_1
- 这是一个VHDL的程序，计数器程序实现输入输出从1到8的记数，完成这样的一个功能。-This is a VHDL program, program counter input and output from count 1 to 8, to complete such a feature.
FSM
- FSM source –Next state calculation –Output calculation –State transition
DiSyLab3
- A vhdl design of a control unit 2
elecfans.com-
- FPGA很有价值的27实例.rar 包括 LED控制VHDL程序与仿真 2004.8修改.doc-vhdl example
zhangxing
- 利用vhdl语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s-Digital alarm clock, clock and alarm functions
spi
- Altera Cyclone SPI-slave vhdl module
test_uart
- 基于FPGA的串口通信实验,能将PC发给FPGA的信息原样返回给PC机-FPGA-based serial communication experiment, the information sent to the FPGA can PC as it returns to the PC
VHDL_CAIDENG
- 基于altera de2的流水灯循环程序，使用VHDL编写。-Based on a de2 Lantern cycle, use of VHDL
VHDL
- VHDL课件，教程。英文版。introduction，language，hardware design。-VHDL courseware, Lecture notes. English. introduction, language, hardware design.
spi_controller
- SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top modul
SobelEdgeDetection
- Sobel Edge Detection Algorithm in VHDL
AUTORING
- 自动打铃系统 附带时钟 定时打铃 整点打铃-Auto-play Ling System