资源列表
DE2_UserManual
- DE II board user manual
Simplified_Physical_Layer_Spec
- simplified physical layre specs of SD card
digital_watch
- Verilog code of digital watch
RAM_BLOCK
- Ram block code in Verilog
ripple_counter
- Ripple Counter Code in Verilog
dds
- VHDL的DDS代码，也就是直接数字式频率合成器设计-The DDS VHDL code, which is Direct Digital Frequency Synthesizer
songer
- VHDL的音频发生器设计！！很实用的哦，在现在的数字时代起着重要的作用-VHDL design of the audio generator! ! Oh, very practical, in the present play an important role in the digital age
sinout
- VHDL的正弦信号发生器设计，功能大家都知道了！！就不用说了呀-VHDL design of the sinusoidal signal generator, function as we all know it! ! Needless to say it! !
code_lock
- 本程序是基于vhdl的4位电子密码锁设计，能够预先设置、修改密码，密码输入错误、超时报警！-This procedure is based on the 4-bit vhdl electronic locks designed to pre-set, change thess paword, the password input error, timeout alarm!
fir_lowpass
- 硬件语言实现数字低通滤波器，使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
fulladder
- full_adder verilog module
total
- 8位抢答器VHDL描述-VHDL descr iption of an 8-bit Responder