资源列表
I2C-BusDesign
- 本程序给出了完整的I2C设计工程文件及VHDL源代码-This procedure gives the complete design of the project file and I2C VHDL source code
SOPC
- 能显示时、分、秒，24小时制；可设定夜间某个时段不报时；-Can display hours, minutes, seconds, 24-hour system can set a time at night is not the newspaper
deng
- 彩灯电路，Quartus7.2，幕布式，移动式-deng Colourful light electric circuit, Quartus7.2, act cloth type, ambulation type
iiscode
- 用Verilog写的一个简单的IIs控制器，分为clkgen时钟分频模块和transcon传输控制模块。其中transcon模块主要部分为一个有限状态机实现的满足IIS标准的输出。 另附一个简单的Testcase以及得到的波形。-Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and syn
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
DDS_100325(13)_success
- QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi
Verilog
- Verilog语言练习与讲解中文版.pdf-Verilog language exercises and explain the Chinese version. Pdf
frenquent
- 分频器的一些程序。包括整数分频，小数分频，我感觉非常好的资料，不敢私自分享。特拿出来分享。希望想学习的好好参考下，肯定会有所感悟。-Divider of some procedures. Including the integer frequency, fractional, and I feel very good information, not privately share. Point out to share. They want to study more carefully th
PILILED
- For pili light implement , with verilog design method.-In ASIC flow, use verilog to insted of 8051 ASM code design.
Ham_Code
- Hamming code is implemented by ASIC design method.-With verilog design way, we can check error control code with hamming code .
div_fru
- 介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。-Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not
8250
- Verilog HDL写的串行接口控制器82-Written in Verilog HDL serial interface controller 8255