资源列表
carry_look_ahead_adder
- Carry look ahead adder
saopin
- 扫频输出信号源，扫频范围可修改，verilog语言。-Sweep frequency output signal source, sweep frequency range can be modified, Verilog language.
dgnszsz
- 多功能数字钟，在quartusII软件平台上实现的verilog源代码。大家试试看。-Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.
ex1_clkdiv
- 这个实验可以说是verilog入门最基础的实验了，我们不做太多的理论分析，实践是硬道理。 当CPLD的I/O（ FM）为低电平时，三极管导通， 蜂鸣器发声。-This experiment can be said to be the most basic experiments verilog entry, and we do not do a lot of theoretical analysis, practice is the last word. When the CPLD' s
FPGAlow-costIntelligentDisplayModule
- FPGA和嵌入式处理器实现低成本智能显示模块-FPGA and embedded processors for low-cost intelligent display module
EXP4_sec
- 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0，当计数到9时，下一次数值为0。利用Verilog HDL语言，编程实现上述功能。-Stopwatch
RS232_transmitter
- 基于VHDL的串口发送源程序，Altera cycloneII系列-The source program of RS232 transitter based of VHDL
Sintab_Altera
- 在利用Verilog在FPGA平台上输出正弦波，实现芯片为Cyclone II 484C8，有管脚分配
UART-SPI-I2C-VGA
- 里面有i2c,uart,spi的代码，也是从别的地方下的觉得还不错,，与大家分享一下，做个参考-I2c, uart, spi code inside, but also from elsewhere feel pretty good, and we share with you, to be a reference
freqtest_dec
- 用VHDL设计了一个频率计，给出了各模块的详细源码，并给出了注解，对初学者及课程设计有帮助。-VHD designed with a frequency counter, gives the details of each module source code, and gives notes on programs designed for beginners and helpful.
VGA_controller
- 基于altera FPGA的 VGA显示控制-Altera FPGA-based control of the VGA display
dfgg
- 请先删除编译后的debug/release目录以减少压缩包大小-compiled the debug / release directory to reduce the size of compressed