资源列表
Digital-pulse-counter-design
- 《数字脉搏计数器设计》，电子设计的文档！-Digital pulse counter design, electronic design document!
the-taxi-meter
- 利用MAX plus10.2对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。-The MAX plus10.2 the design of the taxi meter VHDL code simulation, and FPGA digital experimental system To implement the control. This is the decoding module
DE2_lcd_clk
- 用VHDL写的在DE2开发板上的LCD实现的秒表程序-DE2 development board LCD stopwatch program written in VHDL
miaob
- 电子秒表，FPGA实现,本科某课程设计，程序注释非常详细，-FPGA TIME-COUNTING
my_uart
- 数据收发器，串口模块，可使用串口调试小助手来进行数据收发，验证模块的功能-Data transceiver, serial module, you can use the serial port to debug his assistant to send and receive data, verify the functionality of the module
fft
- fft的用VHDL的一个fpga程序，绝对经典！-fft of an fpga with VHDL program, absolutely classic!
pianoend
- 用8×8点阵显示“1 2 3 4 5 6 7”七个音符构成的电子琴键盘。其中点阵的第一列用一个LED点亮表示音符“1”，第二列用二个LED点亮表示音符“2”，依此类推-88 dot matrix display " 1 2 3 4 5 6 7" of seven notes of the piano' s keyboard. The first column of the lattice with a LED lit notes, " 1" , notes
ug_fifo
- 可综合的FIFO存储器，全部在一个压缩包中，测试过，可以使用．-be integrated FIFO memory, all in a compressed package, tested, can be used.
state
- verilog 应用状态机设计的序列检测器-verilog ，state machine
uart_tx
- It is an UART interface that is written by me in VHDL to receive and send datas from/to FPGA.
DDS小数分频
- 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.xml ...........\..\DDS.cmp.
4670.TLK1221
- tlk1221的芯片资料，主要是有tlk1221芯片的电路应用实例。(Tlk1221 chip information, mainly tlk1221 chip circuit applications.)