资源列表
Verilog
- VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等-VHDL Verilog 系统仿真实验 流水灯 加减法 计数器 序列检测 编码器 解码器等
Revised_Verilog_code
- 简弘伦：Verilog HDL IC设计核心技术实例详解 源代码,更新版本-Honglun Jian, Revised Edition. Source coude of " Core Techniques of IC design"
dac
- MFSK调制与解调，max-plus2工程,常见的通信专业课程设计-MFSK modulation and demodulation, max-plus2 engineering, common communications professional curriculum design
zhong
- 数字钟，实现整点报时以及校时功能，烟大数字逻辑课程实验。-Digital clock, realize the whole point timekeeping and school function, smoke large digital logic course experiment.
undistort
- floating point arthematic function with verilog code
all
- 利用VHDL程式達到上數9999 並且有遮沒+防彈跳功能，是個很好又實際的程式。-Reached on the use of VHDL program and the number of 9999 did not cover+ anti-bounce function is a very good and practical programs.
virtex-5电路原理图
- virtex-5电路原理图
mimasuo2S50
- 8位密码锁的实现，初始状态默认为密码正确，密码输入正确方可设密码，以后必须按对密码才可重设-8 password lock the realization of initial state defaults to the correct password, the password can input the correct password. After the password must be re-established before
barrel_shifter
- 自己写的环形移位寄存器的verilog程序，功能是由输入控制左移的位数，实现循环左移。-Write your own ring shift register verilog procedures, functions are controlled by the input number of digits left to achieve the left circle.
01
- 利用语言实现时钟数码管显示，适于初学者学习-The use of language to achieve clock digital display, suitable for beginners to learn
AD6635
- The AD6635 is a multimode, 8-channel, digital Receive Signal Processor (RSP) capable of processing up to four WCDMA channels
PS2controller
- 基于Verilog语言的PS2控制和显示程序，完成Basys开发板上对PS2端口的控制，和数码管显示-Verilog-based Voice of the PS2 control and display program, complete Basys PS2 port on the development board control, and digital display