资源列表
ADC_DSP_FIR_Filter
- 改程序实现了通过dspic30f5015内部ADC模块对模拟量进行采集，之经过FIR滤波，-Reform program implemented by the internal ADC module dspic30f5015 analog acquisition, the after FIR filtering,
piaobiao
- 数字跑表，具有复位、暂停、秒表计时等功能。有三个输入端，为时钟输入(clk)、复位(clr)、启动与暂停(pause)。-Digital stopwatch, with reset, pause, stopwatch functions. There are three inputs for clock input (clk), Reset (clr), start and pause (pause).
jian2
- 1、 掌握VHDL的结构以及实例的编程； 2、 学会使用QuartusⅡ平台的开化； 3、 设计一个2位BCD码加法器。
Day2
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
rs232_UART
- RS232通讯程序，已经调试通过，可以直接使用。-RS232 communication program, has been through debugging, can be used directly.
dth
- sdsg er3wresdg test w45 24at eu y t545 4 4t 4
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
sequencedetector
- verilog code for 3 bit sequence detector
i2cmmm
- i2c 可以直接进行综合-i2c rrrrrrrrrrrrrrrrrrrr
XSA-P2MOUSE
- simple ps2 mouse vhdl project
uartfifo
- 基于FIFO的串口发送机设计。主要实现一个串口发送器功能，该发送器的数据是从FIFO 中读取的。也就是说，只要FIFO 中有数据，串口发送器就会启动，将数据发送出-FIFO-based serial transmitter design. A serial transmitter function of the transmitter data is read from the FIFO. In other words, as long as there is data in the FIFO,