资源列表
Digital_clock11
- 基于FPGA芯片设计多功能数字钟，具有任意时刻定时闹钟，有分频器，计数器，等等模块构成-Regular alarm clock based on the FPGA chip design multifunction digital clock, any time, divider, counter modules
rom
- 一个ROM读数据代码，简单，一目了然，一起学习-A ROM read data code, simple, clear, along with learning
7shumaguanEDAfangzhen
- 用VHDL语言的七段数码显示译码器设计 已仿真出结果 用来学习7段数码显示译码器设计；学习VHDL的CASE语句应用及多层次设计方法。-VHDL language of seven-segment display decoder has been designed simulation results were used to study a 7-segment display decoder design learn VHDL CASE statement applications and
ound
- FPGA与PCI_E总线在声靶控制器中的应用-FPGA and PCI_E bus controller of the target sound
Verilog_PS2
- 使用verilog，键盘输入，显示其扫描码在数码管上。-Using verilog, keyboard input, indicating its scanning code on the digital control.
ex11_sram
- sram全部程序及相关文档 测试通过，实验文档纤细说明了实现步骤-sram and the document how to relieaz it
PracticalComputerVisionUsingC_diskette
- The diskettes associated with this book contain most of the code, organized by chapter, and a set of sample images. The code will compile using Borland Turbo-C on an IBM PC or compatible having a VGA card. The basic code for the Alpha
altera_up_avalon_vga
- 用avalon控制的 vga显示程序 Verilog 语言编写-Controlled by avalon vga display program written in Verilog
uart_receive_send_verilog
- 自己写的串口quartus8.0工程，串口收发virilog程序，在EP1C3T144C8芯片验证运行成功，时钟频率50Mhz，波特率115200.-Own write serial quartus8.0-engineering serial transceiver virilog program runs successfully verified, in EP1C3T144C8 chip clock frequency of 50Mhz, baud rate 115200.
test
- 基于cordic算法的VERILOG HDL的设计，仿真和验证都正确，是一个开根号的算法。-cordic， verilog
S6_LCD_VHDL
- FPGA实验工程源代码,梁祝音乐，跑马灯-FPGA source code of some experiment
FPGAdigitaltimer
- 本设计要实现一个具有预置数的数字钟的设计,具体要求如下: 1. 正确显示年、月、日 2. 正确显示时、分、秒 3. 具有校时,整点报时和秒表功能 4. 进行系统模拟仿真和下载编程实验,验证系统的正确性 -designed to achieve this with a number of preset clock design, and specific requirements are as follows : 1. Display correctly, , 2. d