资源列表
openfire2_latest[1].tar
- VGA 到LVCD verilog 源码，接口为RGB4:2:2 模式可以选择-The OpenCores Enhanced VGA/LCD Controller Core provides VGA capabilities for embedded systems. It supports both CRT and LCD displays with user programmable resolutions and video timings, thus provid
S2_LED
- FPGA实用程序，测试led，开发环境为Quartus II 8.0 (32-Bit)，已经测试ok，供大家参考学习-FPGA utility, the test led, the development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
S6_MUSIC
- FPGA实用程序，测试music乐谱，使用PWM驱动蜂鸣器，开发环境为Quartus II 8.0 (32-Bit)，已经测试ok，供大家参考学习-FPGA utility to test music score, the use of PWM drives the buzzer, the development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
S3_SEG7DISP
- FPGA实用程序，测试LED数码管显示，开发环境为Quartus II 8.0 (32-Bit)，已经测试ok，供大家参考学习-FPGA utility to test LED digital display, the development environment for the Quartus II 8.0 (32-Bit), has been tested ok, for your reference learning
DSP2812SCH
- 这是前面几个FPGA例子的开发板原理图，是DSP&FPGA综合性开发板，供大家参考学习-This is the first few examples of FPGA development board schematics, a comprehensive DSP & FPGA development board, for your reference learning
VHDL_FPGA
- 学习FPGA的好资料。适用于初级读者。其中既有硬件部分，又有软件部分-a program for learning FPGA
vhdl[1].tar
- 某高校的FPGA作业，是大家学习FPGA的绝佳参考资料-a program for learning fpga
Electric_clock_design_with_VHDL
- 本次设计的电子钟具有正常计时，时间手动设置，闹钟，秒表四种功能，能够输出24小时制的时间。 电子钟上电reset后，即以默认设置的时间00：00：00开始正常计时，工作模式为计时模式。mode键是工作模式切换键，按照计时—设置—闹钟—秒表四种模式一次切换。在正常计时模式下，按一下mode键切换至设置模式，left和right键用来调整小时或分钟使能被设置，up和down键用来调整时间，调整单位是1；设置好时间后按start_stop键确认（此处使用start_stop键作为ok键使用）。闹钟
IP_CORE_4
- An example of using VHDL IP cores for the Spartan 3A Stater Kit
FFT
- 基4的FFT的VHDL实现 基4的FFT的VHDL实现-fft processor
Encoder_3
- A simple encoder schematic, described in VHDL and tested on a Spartan 3A Starter Kit board by Xilinx
my_uart
- 使用VHDL描述的简单的串口通讯，在Quartus上验证过，包含所有文件-this is a simple uart