资源列表
ram_latest
- VHDL实现CISC模型微处理器设计（含有rom和ram）本程序实现的是输入10个数，输出最小负数-VHDL model to achieve CISC microprocessor design (with rom and ram) to achieve this procedure is the number of input 10 and output the smallest negative
interleaver
- 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
verilog
- 华为的VERILOG HDL语言的精简培训教程，是值得一看的好东东！-IT IS VERY GOOD FOR BEGINNING
3_8_DISPLAY
- vhdl实现3－8译码器，并通过7段数码管显示程序-vhdl decoder to achieve 3-8, and by 7 segment LED display program
TIMER
- 这个为倒计时时钟显示控制实验例子程序，大家可以参考-The countdown clock shows control experiments for the example program, we can refer to
test
- 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to
cpldkeyboard
- cpld利用学习机键盘输入数据，并在数码管显示出来，而且数码管显示位置可以选择-cpld use of learning machine keyboard input data and displayed in the digital control and digital display location option
da
- 用FPGA实现DA功能，同时控制液晶显示波形。-FPGA Implementation with DA function, while controlling liquid crystal display waveforms.
memory_testbench_systemverilog
- memory_testbench using systemverilog
Azhar_fg
- Video information collection and processing
mips
- cpu---risc---mips源代码-cpu---risc---mips
ddr2_sdram
- xilinx spartan2 fpgaddr2控制代码，使用verilog编写，可综合-xilinx spartan2 fpgaddr2 control code, using verilog preparation, can be integrated