资源列表
DESalgorithmforfpgadesignsata
- 利用fpga接sata的方案，在fpga进行des加密，难得的参考价值-Sata using fpga access program, conducted in fpga des encryption, unique reference
uartvhdl
- 串口协议的vhdl实现，经过验证，可以直接使用-Vhdl serial protocol implementation
vhdl2
- This a useful book when you are learning VHDL.-This is a useful book when you are learning VHDL.
flag
- vga is video graphics
clock
- 用Verilog语言实现一个时分秒及时的时钟-Verilog language with a time clock when the minute and second
AD1674
- This is an interface in HDL for the AD1674 ADC converter.
MLAW_LINEAR_CONVERTER
- This a HDL implementation of G711 MLAW to LINEAR and vice versa converter. Uses very less resources. -This is a HDL implementation of G711 MLAW to LINEAR and vice versa converter. Uses very less resources.
ALAW_LINEAR_CONVERTER
- This a HDL implementation of G711 A-LAW codec. It converts LINEAR to ALAW and vice versa. -This is a HDL implementation of G711 A-LAW codec. It converts LINEAR to ALAW and vice versa.
Descrierea_comenzilor
- Translation of the datasheet of the UC1610 GLCD controller
sdram_hr_hw
- SDRAM 读写控制检测Verilog源代码程序。-SDRAM read and write Verilog source code control testing procedures.
8051vhdl_ip_core
- 8051完整ip内核Vhdl源代码程序。-8051 ip core Vhdl complete source code program
TRDB_LCM
- DE1/DE2的TRDB_LCM驱动Verilog源代码。-DE1/DE2 of TRDB_LCM drive Verilog source code.