资源列表
digital-clock
- 基于fpga软件的数字秒表设计，非常有用的教学程序-Digital stopwatch design based on FPGA Software, very useful teaching program
JTAG_CPLD_project_1.pdf
- JTAG_CPLD_project source VHDL code ，适用于开发JTAG接口。此工程使用Altera EPM570 MAX II CPLD，包含硬件和软件描述。-JTAG_CPLD_project source VHDL code, suitable for the development of the JTAG interface. This project using the Altera EPM570 MAX II CPLD, includes hardware a
lineardecoder
- 7,4汉明码的译码程序，条理清晰，易读易懂-7,4 Hamming code decoding process, the clarity, easy to read and understand
rxtx
- 串行通信程序，程序稳定可靠，分为好多模块代码写的不错，值得参考，-Serial communication program, the program is reliable, divided into a lot of module code written well worth considering.
fenpin_odd
- verilog HDL写的6分频程序，通过48MHz晶振分出8MHz频率-6 divided by program Verilog HDL written separation of 8MHz frequency by 48MHz crystal oscillator
ram-and-fifo
- ALTERA公司的一些关于RAM，FIFO等IP核的技术文档，对用到IP核存储设备的读者很有用！-ALTERA Company RAM, FIFO IP core technical documentation, readers used IP core storage devices useful!
sourcecode
- 《FPGA嵌入式项目开发三位一体实战精讲》一书的程序代码-The FPGA embedded project development trinity combat succinctly book code
BCD
- Verilog hdl编写的二进制转BCD码程序-BCD binary switch program written in Verilog hdl
seg71
- Verilog HDL编写的7段数码管显示程序。-7-segment LED display program written in Verilog HDL.
serial
- Verilog HDL编写的串口通信程序。-The Verilog HDL written serial communication program.
state-machine
- Verilog HDL编写的简单状态机程序。-The Verilog HDL written a simple state machine program.
FPGA-experiment
- fpga经验总结，fpga系统设计的主要思路和方法初探-the fpga Experience fpga design ideas and methods of the