资源列表
Verilog123
- cpld 实现于电脑的串口通信，跟大家分享下-The cpld realize on the computer' s serial port communication, to share with you the next
mux2to1
- mux 2 to 1 verilog code. It may be good for you !
Mux8to1
- mux 4 to 1 verilog code. It may be good for you !
Mux32to1
- mux 32 to 1 verilog code. It may be good for you !
Adder32Bit
- Adder 32 bit in MIPS microprocessor.
FPGA-dianziqin
- FPGA电子琴的源代码的描述，非常的好，同学们如果需要请下载-Descr iption of the FPGA source code of the keyboard is very good, students need to download the
UART_TX
- UART收发，verilog语言，测试成功-UART transceiver, verilog language, the test is successful
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
NIOS_develop_source_code
- 基于NIOSII核的多种功能性开发源代码，对于学习NIOSII之上的编程有很大的参考和学习价值-Developer source code for a variety of functions based on NIOSII nuclear, great reference and learning the value of programming learning NIOSII top
DATA_SEND1
- 基于w5300的以太网数据传输的vhdl程序-Ethernet data transmission based on w5300 VHDL program
RISC_CPU
- 1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。 在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备 对总线写操作时，在第3.5个时钟周期处，建立写的地址，第
microcode
- 任天堂nes系统 中央处理器部分代码，希望大家能用得着-Part of the code of the Nintendo nes system central processor