资源列表
CLOCK
- Clcok Source Code in VHDL fo FPGA Devices, Display Time in Seven Segment
SIREN
- An Alarm Project Writen in VHDL for FPGA Devices
SCA126T-100130
- SCA126T 是瑞芬科技针对工业现场控制领域推出串口输出型双轴倾角传感器，内置高精 度16bit A/D 差分转换器，通过5 阶滤波滤波算法，最终输出双方向的倾角值。 接口可选RS485；RS232 或TTL 电平。由于内置了ADI 公司的高精度数字温感器，所以 输出角度在工作温度范围内都得到了再次修正，保证产品在低温与高置环境下的高重复性。 高的输出速度能达到20 次/秒。产品属于真正工业级产品，性能可靠稳定，扩展性好， 多种输出可供选择。适合应用于各种恶劣工业控制环境-
TV
- an analog video input to VGA video output Verilog
giaotiepnt
- an analog video input to VGA video output Verilog
clk_teiler
- clk for system fpga to pci card-clk for system fpga to pci card
pci_steuerung_target
- vhdl code for card pci to fpga
pci_steuerung_master
- vhdl code for card pci to fpga
fpga_A
- vhdl code for card pci to fpga
eeprom_out
- vhdl code for card pci to fpga
ds1621_latest.tar
- DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and
color_converter_latest.tar
- The main purpose of the core is a color transform tasks such as CIE XYZ<->RGB, different RGB<->RGB and RGB<->YCbCr operations. The main part of color conversions from one to another color system concludes in 3x3 matrix multiplicatio