资源列表
UART_source
- 用VHDL编写的UART源程序，请需要的朋友下载-VHDL source files prepared by the UART, please download a friend in need
00-99-counter
- 00－99 计数器 00－99 计数器 -00-99 counter
display
- 单片机实现的跑马灯和数字钟点显示，跑马灯速度可调，可以暂停-MCU marquees and digital hour display, marquees speed adjustable, can be suspended
Delay_LEDs
- this a protus schematic for displaying the letters-this is a protus schematic for displaying the letters
dds
- 直接数字频率合成器 有完整的代码 有完整的代码-Direct digital frequency synthesizer with complete a complete code of code
pwm
- PWM Verilog HDL原码和底层C驱动，即测试程序，可直接使用
UART-and-FPGA
- 基于FPGA的UART通信控制器 设计与实现持。用到modelsim6.1f环境模拟。-UART communication controller based on FPGA Design and Implementation of hold. Used modelsim6.1f environment simulation.
i2c hdl core
- I2C Hdl code for SOC design and FPGA
clk_div
- 任意整数分频器，通过改变参数，可设置所需要的分频频率和占空比-Arbitrary integer divider, by changing the parameters, you can set the desired crossover frequency and duty cycle
t65
- Full VHDL code for T60 processor-Full VHDL code for T60 processor....
led
- led数码管动态扫描控制，循环点亮，可在keil环境下编译-Dynamic scan control led digital tube, cycle light, in keil compiler environment
Verilog-HDL-intra_prediction
- 基于H.264的帧内预测中4×4块的9种预测方法的源程序-H.264 intra prediction based on 4 × 4 block prediction method of the source 9