资源列表
multi-function-digital-clock
- 基于fpga的多功能数字时钟设计，有预设和报警功能-Fpga-based design of multi-function digital clock, presets and alarm functions
dac
- 基于fpga的数模转换器接口设计，转换数码管上显示的数字电压-Convert the digital voltage is displayed on the digital tube based the fpga DAC interface design,
pcf8563
- I2C总线接口实现，显示pcf8563实时数字时钟的秒，分，可设置报警功能-I2C bus interface implementation, display pcf8563 real-time digital clock, seconds, minutes, you can set the alarm function
the-elevator-control-system
- 基于fpga的电梯控制系统设计，采用双电梯联动的方式-Fpga-based elevator control system design, using dual elevator linkage
FIFO
- 基于vhdl语言的fifo设计，方便你了解先进先出理论-Based on the the vhdl language of fifo design, allowing you to understand the first-in, first-out theory
examples
- 赛林思开发环境下的基本实验例程，方便学习-The basic experiments routines Sailin Si development environment to facilitate learning
altera_modelsim6.1g
- altera_modelsim 6.1仿真时常见问题的总结-altera_modelsim 6.1 Simulation summary of the Frequently Asked Questions
dpll1600e
- 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
cordic
- 实现cordic算法旋转模式的verilog代码-Verilog code for cordic algorithm rotation mode
code_lab5_num1
- Xilinx 的VHDL设计时钟 -VHDL design clock clock the Xilinx Xilinx VHDL design
final
- 洗衣机正反转控制程序，用于洗衣机驱动器的控制-key
EDS_AC_RA_DeviceNet
- Profile Bus 的GSD文件,在调试PLC的时候需要用到-the GSD file for Profi-BUS in PLS debug