资源列表
frequency
- 等精度频率计（FPGA部分），通过单片机发送频率控制字给FPGA，FPGA实现计数，再将计数结果发送给单片机后进行数据处理最后发送到数码管或液晶屏显示待测频率-Precision frequency meter (FPGA part) by the single-chip transmit frequency control word to the FPGA, FPGA, to achieve the count, and then finally sent to the digital dat
DDC_VHDL
- DDS信号发生器，可以生成方波，三角波以及正正弦波等，只要稍微修改下输入数据即可生成任意的波形。-DDS signal generator can generate a square wave, and some small modifications to the next input data to generate arbitrary waveforms.
ipI2C
- IP核的设计与验证，使用I2C进行FPGA与FPGA之间进行通信-Design and verification of IP cores, using I2C communication between the FPGA and the FPGA. .
div_clk_encoder
- 对系统时候进行任意的偶数分频，只要修改几个位置即可，方便移植。另一个是7段数码管驱动程序。使用-System when any even divide, as long as the modified several locations can be easily ported.
FIFO
- FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存 储器的区别是没有外部读写地址线，这样使用起来非常简单，但缺点就是只能顺序写 入数据，顺序的读出数据，其数据地址由内部读写指针自动加1完成，不能像普通存 储器那样可以由地址线决定读取或写入某个指定的地址-FIFO is the abbreviation of the English First In First Out, a FIFO data buffer, the differen
9b93752447d7
- 用verilog 写的 USB 驱动 适用于SOPC IP CORE-USB drive write verilog. For in the SOPC IP CORE
vga_gui
- VGA 的 ip core 编写程序时需要逐点编写-VGA-ip core programming point by point to write
VGA_Controller
- 适用于 Microtronix 的 Lancelot card 的 IP CORE-Microtronix of Lancelot card IP CORE
fszf
- USB 驱动需要用到的源文件 （.h .c 文件）-USB drivers need to use the source file (. H c file)
sdram_mdl
- FPGA 控制SDRAM读写，通过按键控制读写操作，读出之后发送到串口显示到电脑终端。-FPGA to control the SDRAM read and write, read and write operations by the key control to read out is sent to the serial port to display to the computer terminal.
RS_Encoder
- 具有16个校验位的RS编码器，在FPGA上实现。-With 16 RS encoder, the parity bit in the FPGA.
VHDL-key
- VHDL语言程序，具有按键消抖哦，程序比较简单，易明白，欢迎大家下载哦-VHDL language program, with key debounce, the procedure is relatively simple, easy to understand, are welcome to download Oh! ! !