资源列表
32
- 电子琴程序设计与仿真，vhdl编写，实用！-Keyboard programming and simulation, vhdl to write and practical!
fsg
- 自动售货机VHDL程序与仿真，可以直接实现！-Vending machines, procedures and VHDL simulation, which allows direct
ask
- ASK调制与解调VHDL程序及仿真，完全实现，详细！-ASK modulation and demodulation process and VHDL, and simulation, fully realized, in detail!
fsg
- FSK调制与解调VHDL程序及仿真，完全实现！毕业论文实用！-FSK modulation and demodulation process and VHDL simulation, the full realization of Thesis and practical
filter
- 低通滤波器的代码，能够实现低通滤波器的功能，自己写个测试平台就可以仿真了。-The code of the low-pass filter, low-pass filter function, write a test platform can be simulated.
trafficagain
- 此程序是以VHDL来设计真实世界交通灯控制系统。经过下载到FPGA中调试，证明其真实可用。为了方便调用，特地将程序分成两个部分，包括主函数和一个数码管显示子程序。-This program is based on VHDL to design real-world traffic light control system. Been downloaded to the FPGA debugging, to prove its real available. Order to facilitate
L-CBF
- verilog code for lcbf
fifo_module
- 基于vhdl的FIFO建模，主要是用于输入输出数据缓存-Vhdl-based FIFO modeling is mainly used for input and output data cache
divid
- 基于VHDL的divided建模，方便调用，主要是除法运算，用于数据移位-Divided modeling based on VHDL, call the main division operation is used to shift data
muti
- 基于VHDL的乘法器算法建模，主要用于数据移位-Multiplier algorithm based on VHDL modeling, used mainly for data shift
LCD1602four
- msp430给553 LCD1602程序，希望对大家有用-msp430 to 553 LCD1602 program, the hope that useful. . .
clock24
- clk：基准时钟信号输入； sec_narmal:周期为1s的信号输出； sec_s:周期为0.5s的信号输出； sec_m:周期为0.01s的信号输出； sec_h:周期为0.0005s的信号输出；-clk: the reference clock signal input sec_narmal: The cycle of the signal output 1s sec_s: The cycle of the signal output 0.5s sec_m: