资源列表
Maxplus2_74LS161
- 用Maxplus2制作的实现74LS161数字芯片功能，入门级工程。-Maxplus2 made with digital chips to achieve 74LS161 function, entry-level engineering.
mod10asynchro
- this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
hbf-da-timeshare
- This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).
adder_16
- 实现16位加法器功能，使用Verilog语言编程，使用的是数据流形式
lab4_VHDL
- VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.
xor
- implementation of XOR gate in VHDL with rtl view and simulations
decode
- 用Verilog实现汉明码的解码，经测试可以正常使用，且代码简介-Verilog with Hamming code to achieve the decoding, the test can be used normally, and the code
Teste
- rsthghgsh
project
- 含project_基于FPGA与加速度计的体感超级马里奥游戏开发，基于spartan 3A开发板制作的小游戏-Project_ based on FPGA and accelerometer with the body feeling super Mario game development, based on the 3A Spartan development board produced by the small game
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
vim-vhdl
- Vim scr ipt for vhdl coding and vidualisation. Some special features like useful syntaxis lighting included.
decode
- 用Verilog实现汉明码编码，经测试可正确使用，代码简洁-Verilog with Hamming code encoding, the test can be used correctly, the code is simple