资源列表
ec11-test
- 台湾产数字编码电位器EC11的使用测试程序-Taiwan-digital encoder potentiometer EC11 of testing procedures
Ttwo_d_dct_sew
- 二维DCT变换，采用查找表的方法实现算法，分别通过列变换，，再通过行变换，通过加法器乘法器和流水线技术得出更快的结果！ -2D DCT algorithm using look-up table method, respectively, by column transform, and then transform through the line faster results obtained by the adder multipliers and pipelining techniq
chu_ip_drv
- It contains the C driver (.c and .h) files of IP cores in Parts III and Part IV. Since the driver files are not integrated with HAL, the corresponding files must be manually copied to the software application project directory when a core is used i
1
- 设计一个用于篮球比赛的定时器。要求： （1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1； （2）定时器的时间用两位数码管显示； （3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。 （4）输入时钟脉冲的频率为50MHz.(Design a timer for a basketball match. Requirement
帧同步
- 这是一个可以实现帧同步的编码，应用verilog编码(This is a coding that can implement frame synchronization, using Verilog coding)
AES 128 ECB Decryption
- Block mode related AES-EBC Encryption
counter_vhdl
- counter_verilog sur fpga
FirstAndriod
- andriod开发学习演示代码，适合初次初次接触andriod人员的学习-andriod study demonstrates the development code, first initial contact for staff learning andriod
74ALS164
- 74LS164 counter in vhdl. Inside is a "shift register" full of 8 bits. This means that it behaves like a series-parallel converter in introducing clock pulses and data series on the other.
opb_wb
- 这是一个连通OPB和Wishbone Bus的Bridge, 能够让OPB与开源的Wishbone Bus连接通信， 从而使用基于Wishbone的许多开源IP Core
How-to-build-a-custom-FPGA-board
- How to build a custom FPGA board
dianlubaojingqi
- 输入电压超过3V，显示ERR，并报警。电压值可在七段数码管显示，点阵广告屏显示或液晶屏显示-Input voltage exceeds 3V, display ERR, and the police. Voltage values in the seven-segment display, dot matrix screen advertising display or LCD display