资源列表
Verilog_sdram
- Verilog写的SDRAM接口控制资料希望对大家有用！-Verilog write SDRAM interface control information for all of us hope!
ahb_master_latest.tar
- IN THIS WE HAVE AHP bus master for burst data transfer
ahb_mas.tar
- its shows the ip of amba ahb master in vhdl
test_uart_rtc
- RTC程序的编写，是一个主控时钟32768时钟调试-RTC procedures for the preparation, is a master clock clock debugging 32768
General-memory-VHDL-code-library
- 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
clock_divider
- 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed descr iption of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL
DAC
- DAC control the chanel
lab4_VHDL
- 这是基于VHDL的编程练习，适合于初学者学习VHDL编程，通俗易懂，简明扼要。
Op-Amp-Model(VHDL-AMS)
- 模拟信号模型-运算放大器模型Op Amp Model的VHDL-AMS程序-Analog signal model- op amp model Amp Model VHDL-AMS Op program
FIFO_ise11migration
- fifo buffer vhdl code
zhuan
- 一个关于串并和并串转换的verilog的工程，代码简洁易懂-this is a sample program project for transformation
DES_IP
- 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed