资源列表
sin
- 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的
labant4
- Circuito antirrebote realizado con vhdl
async_fifo
- 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
qiangdaqi
- 设计一个四路抢答器。抢答器必须具有互锁功能，同时抢答时每次只能有一个输出有效。同时，抢答时具有计时功能，限定选手的答题时间，在接近规定时间时进行提示，达到规定时间发出终止音。主持人可控制加分或减分。-Design a four-Responder. Responder must have the interlock function, while there can be only one answer when output is active. Meanwhile, the answer,
ISE_lab9_cnt
- excd-1 开发学习板 计数器的实现 数码管显示-count a_t_g led
demo7-uart
- 一个编译好的FPGA+UART源代码,可供学习修改-A compiled FPGA+ UART source for learning to modify
fga
- FPGA的内建自测试的实现FPGA implementation of built-in self test-FPGA implementation of built-in self test
demo7-uart
- FPGA EP2C5的串口代码，FPGA新手学习的很基础的代码-about the FPGA IC:EP2C5 uart code.it is use for the fresh one.
DDRSDRAMverilog
- 本文介绍了sdram控制器的。本文附上了介绍文档，具有详细的说明。-This article describes the sdram controller. The attached introductory document, a detailed descr iption.
POC
- 用VHDL语言设计一个并行输出控制器POC，作为系统总线个打印机的借口-The purpose of this project is to design and simulate a parallel output controller(poc) which acts an interface between system bus and printer. The Altera’s Maxplus II EDA tool is recommended and provided for simul
spi_slave_latest.tar
- SPI IO 核，非常好用！SPI IP core ，good for use,可用于SoC以及其他模块-SPI IP core ，good for use