资源列表
LIP6801CORE_audio_block
- Audip Block Verilog sourc code
ad
- fpga ad verilog language
CrossClock
- This paper explores the fundamentals of signal synchronization and demonstrates circuits a designer can use to handle signals that cross clock domains!
UART
- 已经过调试成功的fpga串口模块，verilog编写-Has been successful commissioning of fpga serial module, verilog write
I2C
- I2C总线源码，用于I2C总线编程设计-I2C bus source code for I2C bus programming design. . . .
FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
MP3_in_CycloneII
- 在FPGA中实现MP3的解码，verilog的，带说明文档。-In the FPGA to implement MP3 decoding, verilog, and with documentation.
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_s
FPGA-AND-FIR
- 基于FPGA的FIR滤波器设计与仿真文讨式算法系统的基本原理采用分布式算法-FPGA-based FIR filter design and simulation-type algorithms of the text discuss the basic principles of a distributed algorithm
Watch
- 秒表功能电路,实现起动、停止等秒表计时功能。-Stopwatch function circuit, start, stop, etc. stopwatch function.
ddfs
- 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.