资源列表
2C35F672_FFT
- 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。
Altera_2C35F672_FFT_Verilog.RAR
- Altera芯片2C35F672实现FFT_Verilog代码。-Altera chip 2C35F672 achieve FFT_Verilog code.
caiseqianbihua
- 彩色铅笔画的绘制过程，运用交互式着色的方法-Colored pencil drawing process, the use of an interactive method of coloring
demo7-uart
- quartus 串口程序 可以通过开发板的串口对FPGA进行读写操作-the quartus serial program can development board through the serial port on the FPGA to read and write operations
LCD
- EP2C8Q208_Quartus_V8.0 基于FPGA实现LCD VHDL代码-EP2C8Q208_Quartus_V8.0 FPGA-based implementation LCD VHDL code
adder
- FPGA的adder程序，例程包含源文件。对大家学习FPGA很有用。-FPGA adder program, the routine contains the source files. FPGA is useful for everyone to learn.
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码，可用作IP核使用，已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
player
- 这是我利用Verilog hdl语言写的关于音乐播放器的程序，其中还包括了仿真结果，该播放器播放的是梁祝，希望对学习Verilog hdl的同学有所帮助-This is what I use Verilog hdl language program written on the music player, which also includes the simulation results, the player is Butterfly, I hope to learn Verilog hdl
DEMO3_KX8051_GPS_FTEST_2C5
- 此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
VGA
- VGA显示代码 分辨率为800x600 只要稍微改一下参数 可改变分辨率-VGA display code resolution for the 800 x600 as long as a little bit change the parameters can change resolution
ADC
- analog to digital converson programmed in VHDL
fashengqi
- 实现了信号发生器的功能，可以产生任意波形-Functions to achieve a signal generator