资源列表
wtut_vhd
- spartan 3E 1600开发板的秒表计时器源程序，VHDL语言-source code of timer on spartan 3E1600 development board in VHDL
RS232_COMPLETE
- Communication RS232 between Hyperterminal PC to FPGA Spartan 3E
CPLD-FPGA-project-doesnt-fit
- CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？解决方法-CPLD/FPGA编译时提示“project doesn t fit! do you wish to override some existing settings and/or assignments？”
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)
priority_decoder
- Verilog Code for priority decoder
CPUwithout-cache
- 5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!
Intro-VHDL-3-part1
- intro VHDL part 3 section 1, electronic enginering
maxII_spi
- MAXII SPI interface with testbench
clock_1
- 简易数字钟，使用VHDL语言编辑，简单设计，容易学习用
dianziqin
- 主要是基于FPGA的小实验，关于电子琴的设计和相关资料还有代码，具有一定的参考价值-FPGA-based experiment has certain reference value, keyboard design and data as well as code
Mouse2
- mouse led program module VHDL
RS232
- RS232与FPGA的通信程序，经过QUARTUS II 7.1的测试，结果正确-RS232 communication program and FPGA, QUARTUS II 7.1 test results, correct