资源列表
t65
- Full VHDL code for T60 processor-Full VHDL code for T60 processor....
clock
- clock example for xilinx spartan 3 starter board-clock example for xilinx spartan 3 starter board....
top
- PLD大赛 扫频仪的verilog源码，实现了数字鉴幅鉴相功能，很有参考价值-PLD Series Sweep of the verilog source code, to achieve the digital Kam amplitude phase function, a good reference
m_decoder
- 恢复以曼彻斯特编码格式输入的mdi信号成实际数据并存储在双端口RAM后以中断方式通知DSP读取数据，所需双端口RAM程序可以从相应的FPGA编译系统中产生-A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required du
DE2_Default
- 延时一个 时间通过QUARTUS环境编写VHDL代码-delay a time
simplecon
- 基于verilog语言的简单的控制器 实用很方便 适合初级学者-Verilog language based on a simple controller is very convenient and practical for primary scholars
jiuhuche
- 基于fpga的简单救护车 简单实用 初学者的好材料-Fpga-based ambulance simple and practical simple good material for beginners
sin
- 基于verilog的正选函数 简单实用 初学者的好材料-Verilog function based on the simple and practical choice for beginners is a good material
hdlc_rs
- 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual pr
m_encoder
- 将写入的数据用曼彻斯特码格式从meout口输出，所需内部存储单元可根据所使用不同的FPGA类型由相应的编译软件产生所需双端口RAM模块-The data will be written by Manchester code format from meout port output, the required internal storage unit can be used according to the different types of FPGA Compiler software f
muil
- 基于verilog的乘法器 简单实用 初学者的好材料-Verilog multiplier based on simple and practical good material for beginners
simple_register
- 基于verilog的简单寄存器 简单实用 初学者的好材料-Register based on a simple verilog simple and practical good material for beginners