资源列表
uart1_success
- 可以实现电脑和FPGA的串口通信，传送的数据在数码管上显示-Computer and FPGA serial communication, the transmission of data on the digital display
Project-verilog-taxi
- 纯verilog语言编写实现了出租车计费系统的打包好的quartus ii工程。-Pure verilog language to achieve a good package quartus ii engineering taxi billing system.
Lab-DigitalLogicReview
- a laboratory exercise that helps to understand the basic logic gates and to gain a hands-on experience with them.
FPGA_RS_232
- 这个源码是经过对RS232长时间的研究得到的扩展性代码，主要的功能是计算机发给FPGA数据，FPGA利用这些数据去驱动数码管显示，然后再把数据通过串口传给计算机，通过串口调试软件看到你发给FPGA的数据，建议大家先看明白RS232串口通信协议之后再动手编模块。-FPGA_RS_232
pci_verilog_target
- 这是一个Verilog源代码写的PCI从设备参考设计。-This block is the Verilog source code for the Vantis 32 bit 33Mhz PCI Target Reference Design.
lab9_1_1
- 用verilog模拟一个十字路口的红绿灯。移动信息工程学院实验题-To implement a traffic light in verilog.The experiment of SMIE
DDS_Core_HSpeed_ADDA_C5H
- 基于FPGA的高速ADDA采集工程源代码，是基于ALTERA公司的CycloneⅡ芯片的工程示例。-FPGA-based high-speed ADDA acquisition project source code is an example of ALTERA engineering based company CycloneⅡ chips.
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
xulie
- 基于FPGA的任意序列检测器，其中有序列发生器-FPGA-based detection of any sequence, including sequence generator
12864LCD
- 12864点阵使用说明，寄存器的详细介绍。 希望对有志于该设备开发的人有用。-12864 dot matrix instructions, register details. Want to interested in the development of the device were useful.
VHDL_ALTERA_MAX-EPM570-RS232_USB-TTL
- ALTERA MAX-II-EPM570 VHDL example RS232_USB-TTL schematic 21EDA.-ALTERA MAX-II-EPM570 VHDL example RS232_USB-TTL schematic 21EDA.
DIGITAL_TIMER
- 用FPGA开发的多功能电子时钟，能够设置闹钟，调试-FPGA development of multi-functional electronic clock, set the alarm, commissioning