资源列表
rxd
- 用verilog实现的串口接收程序，仿真通过-Verilog implementation receiver program, through simulation
txd
- 用verilog实现的串口发送程序，和之前的发送程序可以一起使用，仿真通过-Verilog achieve serial transmission program, and before sending program can be used in conjunction with simulation through
FIFO
- 用verilog做的FIFO程序，仿真通过-FIFO procedures to do with verilog simulation by
zz
- 用verilog实现的PS2和VGA程序，仿真通过-PS2 and VGA verilog implementation of the program, through simulation
isp
- 关于在线编程isp的课件，初学者适用。上课时用-Courseware, online programming isp beginners apply. Class
sram_bridge
- 多用户访问SRAM，使用开关切换，包括数据总线和控制信号，fpga总线桥-Multi-user access to SRAM, switching, and includes a data bus and control signal, FPGA bus bridge
count60
- 基于de2板的数字计时器，使用verilog hdl 语言。很好的新手教程-Based on the the the de2 board digital timer, the use of verilog hdl language. Good newbie tutorial
GCD
- 可以很好的实现求解最大公约数，并且语法结构易懂-Good solving the common denominator, and easy to understand
clock_lcd
- 基于FPGA用verilog实现电子时钟功能,适合初学verilog者-Suitable for beginners verilog verilog achieve FPGA-based electronic clock function
XilinxSpartan3DevelopmentKit-UsersGuide
- sparatn 3 development board user guide and vhdl language reference guide
asy_fifo
- 异步FIFO的实现方法，配源程序和WORD说明-Asynchronous FIFO implementations with source code and WORD Descr iption
DA_64_FIR(TABLE)
- 用DA算法实现的64阶FIR滤波器，在QUARTUS下调试通过-DA algorithm achieved 64 order FIR filter