资源列表
NIOS_II
- NIOS II 开发常见问题，常见的错误提示和解决办法 下载时出现错误-NIOS II development of the frequently asked questions, common errors and solutions
ping_pong_game
- 利用DaltaSigma DAC原理，输出到示波器XY通道，显示亮点作图，实现乒乓球的游戏效果。-with the Using of DaltaSigma DAC principle, the output to the oscilloscope XY channel to display the bright spot mapping table tennis game.
scope_VGA
- 利用IIC接口的4路 ADC max1037，采集思路信号，通过在FPGA内部的构建DeltaSigma DAC软核，在VGA液晶显示屏上显示波形。 -IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.
dlx_verilog
- 使用verilog语音开发的dlx精简指令系统，简单的功能实现，适合初学者学习。-The use the verilog voice development of the dlx Reduced Instruction Set, simple functions, suitable for beginners to learn.
sdram_control
- sdram控制,完整的sdram读写控制代码，操作简明易懂。带模拟输入，可- sdram control.write and read
ss
- verilog语言编写的基于M序列的编解码设计-verilog language design M-sequence-based codec
systolic--matrix-inversion
- DSP算法架构及设计，内容为基于systolic的上三角矩阵求逆电路的实现，里面有详尽的MATLAB/SIMULINK 仿真模型，及HDL代码和在modelsim中的仿真程序，非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
signal_generator
- 信号发生器 可以通过该程序产生对应的波形 用Verilog语言编写实现 希望能对大家有帮助-The signal generator can generate through the program corresponding to the waveform using the Verilog language
FPGA
- FPGA的手册，其中包括430，ds001的功能模块介绍等等。-FPGA manual, including the 430, ds001 the function module is introduced, and so on.
clock_2
- verilog hdl 时钟程序，数码管显示，并可设置闹钟-verilog hdl clock program, the digital display, and can set the alarm
decoder_38
- 38译码器，用verilog hdl 编写-38 decoder, written in verilog hdl
code
- this a vhdl code for ofdm modulator and can be implemented using fpga-this is a vhdl code for ofdm modulator and can be implemented using fpga