资源列表
1602
- 关于LCD1602的谁用说明，说的比较详细，希望对你有帮助-On LCD1602 who use the instructions that detail, you want to help
address_gen
- 基于FPGA使用Verilog语言构成的DDS信号发生器-DDS signal generator based on FPGA using Verilog language constitutes
the-Application-of-FPGAs-for-network
- Summerville写的FPGA在大型网络设备中的具体应用-Summerville write the FPGA in the large network equipment
ds1302
- ds1302的液晶显示程序，cpu 采用的是89c51单片机，显示效果很好-this code is for ds1302 written by C language
11034635826747
- 制作示波器的资料，是是基于FPJA的，在其他地方找的资料-Production of the oscilloscope, is based on the FPJA, in other places to find information
USART
- uart with arm32f103v6
multiprocessor_test
- 基于FPGA的双核处理器实验，相关资料和文档说明-FPGA-based dual-core processor experiments, the relevant information and documentation
RISC-CPU-design
- 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the thre
20120720
- 北京大学信息科学技术学院开设的2012暑期课课程—基于FPGA上的VHDL设计，内容包含全部必选实验的工程文件和仿真波形。-Opened the 2012 Summer Course in Science, Peking University Institute of Technology- based on the FPGA VHDL design, the project file that contains all mandatory experiments and simulation
verilog-fir
- 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
DATA_SAMPLE
- 运用VHDL实现双时钟沿的数据采集（上升沿和下降沿同时采集）-The use of VHDL data acquisition (rising and falling edges of the dual clock edge Acquisition)
niosii_study
- 学习NIOSII时自己下载总结的资料，拿出来大家一起分享-In learning NIOSII to download the summary of the information out to share with everyone