资源列表
5
- 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
sellor
- 数字系统设计，用VHDL语言编程完成自动售票功能-Digital system design, VHDL programming language features to complete the ticket
verilog
- 一些基本器件的实现，包括选择器，计数器，移位寄存器，多位寄存器以及各种测试模块-The realization of some of the basic devices, including the selection, counters, shift registers, a number of registers and a variety of test modules
verilogexample
- 里面包含verilog各种类别的器件的描述以及具体的实现方法-Which contains the verilog descr iption of various types of devices and the specific implementation method
i2s_vmm
- inter IC Sound design with test bench written in Verification Methodology Manual.
EasyFPGA060_Routine_Adder
- EasyFPGA060 加法器实验及文档-EasyFPGA060 adder test and documentation
EasyFPGA060_Routine_SynFIFO
- EasyFPGA060 同步FIFO实验-EasyFPGA060 synchronous FIFO test
EasyFPGA060_Routine_Decoder
- EasyFPGA060 编码器实验及文档-EasyFPGA060 Encoder test and documentation
can2spec
- CAN Specification for people looking forward to design Verification IPs and design IPs
arbiter_priority
- A priority arbiter design which will help some people out there. hope this will be useful for verification engineers
3
- 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K
SystemVerilogforDesignsecondEdition
- ebook for SystemVerilog for Design second Edition