资源列表
SystemVerilog_3.1a
- System verilog manual 3.1
Vhdl
- Very hardware descr iption language tutorial
VerilogHDLexample
- 可综合的VerilogHDL设计实例 ---简化的RISC CPU设计简介-VerilogHDL comprehensive design example can be simplified RISC CPU design--- Introduction---
EasyFPGA060_Routine_RAM
- EasyFPGA060 RAM实验例程与文档-EasyFPGA060 RAM test routines and documentation
EasyFPGA060_Routine_Comparator
- EasyFPGA060 比较器实验例程和文档-EasyFPGA060 comparator test routines and documentation
EasyFPGA060_Routine_Shifter
- EasyFPGA060 移位寄存器实验例程和文档-EasyFPGA060 shift register and document experimental routines
SystemVerilogforVerification2ndEd
- ebook for System Verilog for Verification second edition
da
- FIR滤波器利用串行DA算法实现16阶的，直接可用 ，用VHDL编程-Serial DA FIR filter algorithm using 16 bands, directly available, VHDL programming
VerificationMethodologyManualforSystemVerilog
- Verification Methodology Manual for SystemVerilog
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc
Process_ECG_Signal
- receipt ECG signal and count pick of signal
FPGAImp
- FPGA_implementaion of dadapath for SDR_xilinx