资源列表
decoder4to16
- this is a verilog code for 4 to 16 decoder
ISE_lab2(1)
- xilinx培训资料，配合相应的PDF文件使用-xilinx training materials, with the corresponding PDF file using the
ISE_lab2(2)
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
ISE_lab4
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
Lab1
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
Lab3
- xilinx培训资料，配合相应的PDF文件使用 共20个，先上传一部分，其他的有需要再上传-xilinx training materials, with the corresponding PDF file using a total of 20, first upload a part of, the other the need to re-upload
alu8bit4fun
- its a 8 bit arithmetic nd logical code in verilog it is used for 4 different functions.
mod6asynchro
- this is a code for mod-6 asynchronous counter in verilog.
asynchro2bitupdownneg
- this a verilog code for asynchronous 2 bit up down counter with negative edge triggered.-this is a verilog code for asynchronous 2 bit up down counter with negative edge triggered.
factorial
- verilog code for factorial algorithm
writeandreadSRAM
- 最近操作了诸如UT62256,GM76C256,IS61LV5128 等SRAM 芯片，基本上他们 的时序操作大同小异，在这里总结一些它们共性的东西，也提一些简单的快速操 作SRAM 的技巧。-Recent operations such as UT62256, GM76C256, IS61LV5128 other SRAM chips, the timing of their operation is basically similar, and here summarize some
Chipscope_example
- A easy simple for Xilinx Chipscope Pro, the example shows how to insert cores of VIO, ILA from core generator and verilog code.