资源列表
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
yj
- 开发板的引进配置文件，对学习开发板如何配置引进有很大的帮助。-The introduction of the configuration file development board, the introduction of a great help in learning how to configure the development board.
DE2_70_LTM_Ephoto
- 实现在LTM上显示800*480大小的图片 并且可以触摸实现浏览前一张或者后一张图片-Picture display size of 800 x 480 and can touch a browse before or after the picture on the LTM
DE2_115_CAMERA
- 实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上-DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA
lab5_files
- 关于FPGA ROM与RAM的分析应用及源码-Applications and source code analysis of the FPGA ROM and RAM
lab7_files
- 关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码-Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code
lab7_supplemental_files
- 基于FPGA PS2 的讲解及应用以及举例的大量源码-Based on the interpretation and application of FPGA PS2 as well as the example of a large number of source
lab3_files
- 基于FPGA 计数器的分析及源代码 和怎样写testbench-FPGA counter-based analysis and source code, and how to write testbench
bitsynchro
- 自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。-The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.
divider
- Verilog语言编写分频器，用于数字竞赛式抢答器的设计模块之一-The Verilog language divider for digital contest Responder design module one
decoder
- Verilog编写数字编码器，还有激励输入的代码-Verilog prepared encoder, as well as excitation input code
38-decoder
- 3-8译码器的Verilog硬件语言实现，开发环境是ModelSim-The 3-8 decoder Verilog hardware language development environment is ModelSim