资源列表
ETA-1
- error tolerant addercodings in vhdl
AxiPC
- fpga axi测试程序,可测试符合axi协议的ip核-fpga AXI4 TEST routine，can be used to test ip which is in amba.
diagram
- this is verilog code for euclidean distance transformation
clk
- just division the clock into 2
fulladder
- 全加器 东北大学秦皇岛分校 电子设计自动化 实验-Full adder Northeastern University at Qinhuangdao electronic design automation experiment
uart
- UART design with bist capability
fir_using_FPGA
- 基于verilog的fir滤波，并带matlab仿真
i2sound
- Altera DE2 board demo book thing
FPGA-and-cpu
- FPGA与单片机的串行通信接口的程序设计-FPGA and cpu
a2
- FPGA和单片机串行通信接口的实现 源代码-FPGA and the Serial Communication Interface source code
Frequency_Div
- it is vhdl code for "frequency divider" which was implemented and run in altera quarts- -it is vhdl code for "frequency divider" which was implemented and run in altera quarts- II
up51s010
- 单片机开发，AT89S52计数器小程序-Microcontroller development, AT89S52 counter applet