资源列表
FPGA_interview
- fpga各大公司面试笔试数电部分，内容详尽-number of major companies fpga electrical part of the written interview, detailed
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
project16
- 九九乘法器，对ROM的编写，最终实现在试验箱的数码管上分别显示乘数，被乘数，积-Jiujiushengfa device for the preparation of ROM, and ultimately show the multiplier, multiplicand, respectively, in the chamber of the digital control, product
13898371MXC6202_I2C
- 关于单片机的24c02的有关资料欢迎下载-On the microcontroller 24c02 welcome to download the relevant information
ANDOR
- copuertas logicas and or
实验1
- 用verilog语言实现译码器,包含数据流文件(Achieve decoder with verilog language, including experimental data stream file)
Chapter4
- MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
counter
- 1. 支持递增/递减/增减可配置 2. 支持计数器使能可配置 3. 支持8位计数器(Add mode, subtraction, add and subtract mode, hold mode)
2bit_ecc
- 基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)
programme stabilite
- fbdhtg gfngnhgf j mn nmj,m vgvcx
dayashankar_nair_verilog_2.2.tar
- finite state machine
counter
- 基于FPGA平台的，计数器的简单实现过程(Code based on FPGA, a realization of VHDL/counter)