资源列表
4-to-1-digital-selector
- 4选1数字选择器的Verilog硬件语言实现，开发环境是ModelSim-4 to 1 digital selector Verilog hardware language development environment ModelSim
The-D-flip-flop
- D触发器的Verilog硬件语言实现，开发环境是ModelSim-The D flip-flop of the Verilog hardware language development environment is ModelSim
FPGAdigital-tube
- 单个按键控制四位数码管，按下去，一直按着，数码管显示数字从小到大递增，松开按键，数字实现递减。-Single button control four digital tube, press down, hold down the digital display figures from small to large increments, release the button, digital implementation decreasing.
SDcard
- 一个能用SPI模式的SD读卡程序(VHDL)-A SD card reader program can use SPI mode (VHDL)
uart_tx_rx_baudselct
- 使用verilog语言设计的一个uart的源码，可以进行波特率选择。-A uart source code using Verilog language design, baud rate selection.
vga_pic_70
- VGA控制程序，光栅图像选择性输出，主要是VGA的控制-VGA control program, a raster image of the selective output, mainly the control of the VGA
sdram_48LC16M16A
- 48LC16M16A型SDRAM芯片的FPGA控制器程序-48LC16M16A SDRAM chip FPGA controller program
AD976_6channel
- 软件是适用于FPGA的VHDL程序，目的是用于满足IEC61850－9协议的电子式互感器采样，软件采用的是AD976芯片，能同时进行6个通道的采样。-The software is based on vhdl for FPGA,which is used for electronic transformer fulfil IEC6185-9 protocol.the AD chip is AD976,it works at the state of 6 channels at the same
mu_12channel
- 适用于IEC61850-9-1的合并单元的程序（VHDL），12个通道。-The software is developed for merging unit under IEC61850-9-1 protocol,12 channels.
Xilinx_Workshop-Design_Primer
- Xilinx 大学计划Professor Workshops系列课程-Xilinx Workshop FPGA Digital System Design Primer one
divfreq
- 利用vhdl语言,说明分频程序的工作原理与流程,并结合led进行显示说明其分频效果.-tell us how to divide frequency from main signals via vhdl,and combine with leds to show us detailed information.
beep
- 利用vhdl语言控制蜂鸣器发出指定频率的音律.-by means of vhdl ,to tell us how to control beeper to produce designated frequencies sounds.