资源列表
7segment
- it is 7 segement code
add_gen
- 地址产生器,其采16*15矩阵,行输入,列输出-Address generator, the adoption of 16* 15 matrix, line input, line output
I2C
- I2S interface in VHDL
VHDL
- 除法器 4位除法器 可以编程实现 有启发意义-4-bit divider divider can be programmed instructive
The_veriloghdl_golden_reference_guides
- verilog HDL 黄金指南，对深入学习verilog的人士很有帮助-verilog HDL Golden guid
BusBroadCast
- 公交车报站系统，报站，LED显示 配有SPR模组板，应用简介操作说明，源代码-Bus stop announcement system, to stop, LED display board with SPR module, application profile instructions, source code
1602LCD
- 该程序是1602的verilog程序，该程序采用状态机编写-The program is 1602' s verilog program, the program prepared by the state machine
1111clock
- 多功能时钟，主要有显示时，分，秒。日期，以及时间校正。-Multi-clock, main display hours, minutes, seconds. Date and time correction.
shizhong
- 显示时- 分- 秒、整点报时、小时和分钟可调等基本功能-Show hours- minutes- seconds, the whole point of time, hours and minutes and other basic features adjustable
LCD12864_ST7920
- LCD12864驱动程序 可实现以ARM为CPU的LCD12864的驱动-LCD12864 driver enables ARM-CPU of LCD12864 drive
freqdiv5
- verilog hdl 实现5分频器设计。
11
- 中继群是多路复接群,本文主要讲述在单片机+FPGA结构体系上.利用C51和FPGAdvantage进行模块化软件设计开发。-Relay group is multiplexing multiple groups, this paper describes the structure in the MCU+ FPGA systems of. Using C51 and FPGAdvantage to modular software design and development.