资源列表
DE0_Default
- 友晶公司开发板DE0板载资源的演示程序，新手可以用来看看Verilog语言语法示例-Friends of the crystal plate DE0 onboard resources, developed a demonstration program, novice Verilog language syntax can be used to look at an example
Counter24VHDL
- 用VHDL语言实现24进制计数，具有清零、控制使能作用。-VHDL language with the binary count of 24, with clear control in enabled.
Clock_multipliers
- Clock_multipliers, verilog
Digital_Filter
- Digital Filter, Verilog
Two_port_RAMa
- Mactel公司的TWO PORT RAM的详细使用指南，通过具体的实例，解释的特别清楚，对于使用actel公司的fpga芯片来说帮助很大！-TWO PORT RAM Mactel' s detailed user guide, through specific examples to explain the particularly clear, for use actel fpga chip company is very helpful!
jpegencode
- compress image to jipec
src
- altera 的 fpga 中 fir实现示例，vhdl源码-fpga implementation of fir sample
kuaisufuliyebianhuan_fft_lunwen
- 快速傅里叶变换FFT论文及有关的源程序代码，值得一下，不下实在是浪费了，我找了很久才找到的，有些是一些大牛的毕业论文全文-FFT，VERILOG，some article about FFT and some codes of FFT
quick_fft_1024_8
- 快速傅里叶变换FFT，绝对经典，速度极快，仅仅只有12us，市面上绝无仅有，自己写的，无私奉献出来，希望大家好好利用，好好学习-Fast forious transform,very very very quickly,only 12us,download,no doubt
codeb_generator5
- B码的产生 使用B码进行校时 用来产生B码 以及B码的格式 说明-B generated code when using the B codes school code used to generate B and B code format descr iption
key_xiaodou
- 本例中用状态机实现了消抖电路： 端口描述：clk 输入检测时钟；reset 复位信号；din 原始按键信号输入； dout 去抖动输出信号。-In this case the state machine used to achieve the elimination shake circuit: Ports Descr iption: clk input test clock reset reset signal din original key signal input dout t
jtag_uart
- jtag_uart实现FPGA内部和计算机之间的通信，实时监控方便-jtag_uart achieve FPGA communication between the internal and the computer, real-time monitoring convenience