资源列表
verilog
- 不同Verilog 语言间的差异，以及高版本Verilog语言的特性-Differences between different Verilog language and Verilog language version of the characteristics of high
fallthrough_small_fifo_v2
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小-Synchronous fifo design, simulation has been adopted, written with Verilog, code short
digitaldesignwithPLD
- 可编程的逻辑电路，利用VHDL语言实现的时序和组合电路-Programmable Logic
Synopsys_Graphical_Environment_User_Guide
- Synopsis软件图形界面操作指南，对FPGA/ASIC初学者很有用！-Synopsis software GUI operation guide for the FPGA/ASIC is useful for beginners!
S3_WAVE
- 用Altera公司生产的FPGA仿真SignalTAP程序，用QuarusII6.0编译 -Produced using Altera FPGA simulation SignalTAP program, compiled with QuarusII6.0
state_machine1
- 用FPGA实现的状态机程序，用VrilogHDL实现，希望对大家有帮助-State machines with FPGA implementation process, with VrilogHDL achieve, we want to help
RSIC_CPU
- 该模块为简risc_cpu的verig HDL建模-The module is simple risc_cpu of verig HDL Modeling
music
- 用FPGA实现的歌曲“梁祝”播放程序，用Verilog HDL编写-FPGA implementation with the song " Butterfly Lovers" player, written with Verilog HDL
clock_niosII
- 用Altera公司的SOPC工具NiosII6.0开发，实现hello_world.c，希望对大家有帮助。-Using Altera' s SOPC tools NiosII6.0 development, implementation hello_world.c, hope to help.
elecfans.com-VHDL
- vhdl深入学习教程，包括数据对象以及实例等，本书详细介绍了数据对象类型以及应用方法等-vhdl-depth tutorials, including data objects and example, the book details the data object types and application methods
VHDL_fre_div
- 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of ex
32fir
- 32阶滤波器分布式算法实现的主程序代码,用EP2c35f84c8寄存器速率可达243.55MHz-32-order FIR digital filters: 32 filters distributed algorithm order the main program code, register with EP2c35f84c8 rate up to 243.55MHz