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  1. vsim

    0下载:
  2. multiplexer 16_1 is a multiplexer with 16 inputs and 1 output.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:806byte
    • 提供者:sarv
  1. 1_9_100_cdtv410Cable_Salora-Finlux-MFL

    0下载:
  2. cdtv410 FIREWAVE _9_100_cdtv410Cable_Salora-Finlux-MFL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:997.03kb
    • 提供者:gdchcdn
  1. QAM

    0下载:
  2. its about how to impliment qam on fpga
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:62.67kb
    • 提供者:sundaram
  1. DATA_16QAM_MAP

    0下载:
  2. qam星座映射也qam调制的硬件实现代码详解。用于OFDM下行链路-qam qam modulation constellation is also the hardware implementation code Xiangjie. For OFDM Downlink
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:1.09kb
    • 提供者:李小凡
  1. long_generator

    0下载:
  2. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:1.14kb
    • 提供者:李小凡
  1. spacewar_final

    0下载:
  2. 一款用VHDL编写的飞机大战游戏很好很实用-a game by VHDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:2.93mb
    • 提供者:Donghf
  1. crc

    0下载:
  2. 用verilog实现串进并出的CRC算法-Achieved with verilog into and out of the CRC series algorithm
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:619byte
    • 提供者:santa
  1. lowpowerfir

    0下载:
  2. This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:436.98kb
    • 提供者:Nagendran
  1. viterbi

    0下载:
  2. This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is w
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5.23kb
    • 提供者:Nagendran
  1. cFFT

    0下载:
  2. CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be differen
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:179.33kb
    • 提供者:Nagendran
  1. matrix

    0下载:
  2. 3x3 matrix implementation in VHDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:723.56kb
    • 提供者:Nagendran
  1. modelsim6.0

    0下载:
  2. modelsim 中文使用手册,希望对想学习mldelsim的人有用-modelsim Chinese user manual, and they hope people who want to learn a useful mldelsim
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:379.37kb
    • 提供者:xinghuo
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