资源列表
verilog-example
- 以前用XC3S400AN的fpga开发板做的实验，供新手参考-XC3S400AN fpga development board to do the experiment, for the novice reference
fenpin
- 实现了1到62553的任意分频，且文件中包含测试文件，是个不错的选择。-1-62553 any divide the file containing the test file, is a good choice.
EDA
- EDA培训.分频电路设计.有限状态机.Modelsim仿真.FPGA片内资源利用-EDA training. Divider circuit design. Finite state machine. Modelsim simulation FPGA chip resource utilization
no1
- VHDL做的16位并行输入转16同步串行输出-VHDL to do 16-bit parallel input to 16 synchronous serial output
vga_controller_xilinx
- Xilinx 下的关于VGA接口的程序和工程文件-Xilinx under VGA interface program and project files
V
- 利用FPGA实现一个乒乓球的小游戏，测试可用-FPGA implementation of a table tennis game
MCP3301ADC
- VerilogHDL写的模数转换芯片MCP3301时序，及其ModelSim仿真文件-VerilogHDL write the analog-to-digital conversion chip MCP3301 timing, its ModelSim simulation file
DI
- 这是一个计算占空比的VerilogHDL程序，输入一个待测信号，然后输出Ton,Toff.单位是us-This is a the duty cycle VerilogHDL calculated program to input a signal to be measured, and then outputs Ton, Toff. Unit is us
RAM
- altera FPGA上的RAM源码 单端口结构 -the RAM the source single port structure altera FPGA
PWM
- 基于CPLD的多路PWM的实现，单片机串口传送占空比数据-CPLD-based multi-channel PWM to achieve single-chip serial transmission duty cycle data
dianzhen
- 基于CPLD的32*16点阵的设计，单片机通过串口传送数据-32* 16 dot matrix design, the CPLD-based microcontroller through the serial transmission of data
da.fir
- ADC中滤波器的设计，给那些初学ADC的学生一个参考，老手不要笑我好-The ADC filter design, a reference to those beginner ADC students, veterans do not laugh at me