资源列表
BAO_TP2
- 基于VHDL的简单CPU模型的代码，包含十个原件。已经过仿真河综合-VHDL code for a simple CPU model-based, contains ten originals. River Comprehensive simulation has been
7053590045826
- 基于de2开发板的lcm屏的验证码中的一部分向大家分享-De2 development board lcm screen as part of the verification code to share with you
1226133460_ddvip_5499
- DE2开发板的资料 有用的同学可以开一下 里面关于开发板的内容挺细的-DE2 development board information useful for students to be able to open the inside on the development board is quite thin
8.22-出租车计价器VHDL程序与仿真
- 出租车计价器VHDL程序与仿真,文件是word文件,里面有源程序，程序说明，以及仿真结果图。-Taximeter procedures and VHDL simulation, the file is a word file inside the source code, program descr iption, and the simulation results in Fig.
jiaotongdeng
- 交通灯（非主流简单写法版）：设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替运行，每次通行时间都设为25秒； 要求黄灯先亮5秒，才能变换运行车道；黄灯亮时，要求每秒钟闪亮一次 。-Traffic lights (non-mainstream the simple wording Edition): design an intersection traffic light control circuit, the alternating A the driveway a
Audio_test
- 公司开发板程序E-PLAY-EP4CE40 Audio源码-Company development board program E-PLAY-EP4CE40 Audio Source
TV_VGA
- 公司开发板程序E-PLAY-EP4CE40 VGA图像处理源码 -A Company development board program E-PLAY-EP4CE40 VGA image processing source code
verilog-example
- verilog基础实验，包括篮球计数器，序列检测计等-verilog based experiments, including basketball counter sequence detector
EDA4--3
- 实现的电子钟，资料非常全面，是一次课程设计的大作业，完成的质量很高。-Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.
lab2_Freq_20120510
- 用verilog写的频率计，上课的时候用的。Spartan - 3E开发板。-verilog
elevator
- verilog写的控制电梯的代码。输入多少则计数到那个点后停止计数-elevator controler
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog