资源列表
VHDL100
- VHDL 100例 学习VHDL 和FPGA开发的可以参考一下-VHDL 100 instance learning VHDL and FPGA development for reference
vga_gui
- 在DE2开发板上实现，由于DE2中的SSRAM只有512K，所以640*480*3（byte）的显存是不够的显示结果是经缩放 后的效果，具体可修改Altera_UP_Avalon_Pixel_Buffer buffer模块中的相关代码。 我把代码移植到DE2-70上后，显示的就很正常了。-In the DE2 development board to achieve, due to the SSRAM DE2 only 512K, so 640* 480* 3 (byte)
Impedance_Matching
- 介绍阻抗匹配Impedance_Matching -Impedance_MatchingImpedance_Matching
module001726
- useful stuff for programming in verilog
trlin_celan
- useful project in verilog hdl, named pong
Verilog_HDL
- Verilog经典教程，一共13章，只要读完，绝对通-Verilog classic tutorial，In chapter 13, just read, absolutely
uart
- FPGA模拟串口 实现串口通信，波特率外加-FPAG uart chuankou
code_lock
- 密码锁,内部有密码的初始输入与设置密码,还有密码的鉴定.-Lock, internal code of the initial input and set the password, as well as the identification code.
hamming
- VHDL 实现的海明码编码和校验，可以报错，并且修改错误位，有错误类型码，已包含引脚分配和测试波形-VHDL implementation of the Hamming code and check code can be error, and modify the wrong place, wrong type of code is included pin assignment and test waveform
4_4keyboardscan
- 4*4键盘扫描程序,基于viretex-4开发平台-4*4 keyboard scan ,which is based on the viretex-4 serial .There are many function pin .you must identificate them
displayHELLO
- verilog语言编写，在altera公司的de2实验板上实现八个数码管循环显示HELLO-verilog language, in the experimental altera de2 board to achieve the company' s eight digital control loop shown HELLO
vhdlEXAMPLE
- VHDL 的一些程序，看一下-VHDL